Ring oscillators, particularly fully differential comparator based ring oscillators are difficult to bias and to operate stably with low jitter. Jitter generally means irregularities of the output frequency signal from the voltage controlled oscillator, typically expressed in an output voltage signal, vco. One kind of irregularity is time variation between the moment when successive output cycles reach a particular level. Because of problems of jitter and other signal difficulties, complex circuitry has been developed to accomplish the biasing of differential comparator circuitry in ring oscillators. The design and manufacture of such complex circuitry is expensive. Additionally, some current biasing approaches for differential comparator ring oscillators have employed high transistor count circuitry with high noise injection levels due to amplifier gain incident to comparator biasing. Further, with regulated power supplies, operation of differential comparator ring oscillators over a broad frequency range is difficult.
Accordingly, it is desirable to develop low transistor count ring oscillator circuits which avoid complex biasing schemes in the case of fully differential circuitry, particularly in implementations relying upon a regulated power supply.